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1 ltc1410 12-bit, 1.25msps sampling a/d converter with shutdown s f ea t u re d u escriptio the ltc ? 1410 is a 0.65 m s, 1.25msps, 12-bit sampling a/d converter that draws only 160mw from 5v supplies. this easy-to-use device includes a high dynamic range sample-and-hold, a precision reference and requires no external components. two digitally selectable power shut- down modes provide flexibility for low power systems. the ltc1410s full-scale input range is 2.5v. maximum dc specifications include 1lsb inl and 1lsb dnl over temperature. outstanding ac performance includes 71db s/(n + d) and 82db thd at the nyquist input frequency of 625khz. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 20mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has a m p compatible, 12-bit parallel output port. there is no pipeline delay in the conversion results. a separate convert start input and a data ready signal (busy) ease connections to fifos, dsps and microprocessors. n 1.25msps sample rate n power dissipation: 160mw n 71db s/(n + d) and 82db thd at nyquist n no pipeline delay n nap (7mw) and sleep (10 m w) shutdown modes n operates with internal 15ppm/ c reference or external reference n true differential inputs reject common mode noise n 20mhz full power bandwidth sampling n 2.5v bipolar input range n 28-pin so wide package u s a o pp l ic at i n telecommunications n digital signal processing n multiplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems , ltc and lt are registered trademarks of linear technology corporation. u a o pp l ic at i ty p i ca l complete 1.25mhz, 12-bit sampling a/d converter effective bits and signal-to-(noise + distortion) vs input frequency input frequency (hz) 2 effective bits s/(n + d) (db) 4 6 8 10 10k 100k 1m 10m ltc1410 ?ta02 0 1k 12 74 68 62 56 50 f sample = 1.25mhz nyquist 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ltc1410 0.1 m f + 10 m f differential analog input (?.5v to 2.5v) 2.50v v ref output 10 m f 10 m f 0.1 m f 0.1 m f ?v 5v 12-bit parallel bus m p control lines 1410 ta01 + +a in ? in v ref refcomp agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd dv dd v ss busy cs convst rd shdn nap/slp ognd d0 d1 d2 d3
2 ltc1410 av dd = dv dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................ 6v negative supply voltage (v ss ) ............................... C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) .................................. v ss C 0.3v to v dd + 0.3v digital input voltage (note 4) ............ v ss C 0.3v to 10v digital output voltage ................... C 0.3v to v dd + 0.3v power dissipation ............................................. 500mw operating temperature range ltc1410c .............................................. 0 c to 70 c ltc1410i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number consult factory for military grade parts. put u i a a u log parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 7) l 0.3 1 lsb differential linearity error l 0.3 1 lsb offset error (note 8) 2 6 lsb l 8 lsb full-scale error 15 lsb full-scale tempco i out(ref) = 0 l 15 ppm/ c t jmax = 110 c, q ja = 90 c/w (sw) t jmax = 110 c, q ja = 95 c/w (g) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd dv dd v ss busy cs convst rd shdn nap/slp ognd d0 d1 d2 d3 g package 28-lead plastic ssop sw package 28-lead plastic so wide top view ltc1410cg ltc1410csw ltc1410ig ltc1410isw cc hara terist ics co u verter the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference (notes 5, 6) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v, C 5.25v v ss C 4.75v l 2.5 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 17 pf during conversions 5 pf t acq sample-and-hold acquisition time l 50 100 ns t ap sample-and-hold aperture delay time C1.5 ns t jitter sample-and-hold aperture delay time jitter 5 ps rms cmrr analog input common mode rejection ratio C 2.5v < (C a in = a in ) < 2.5v 60 db
3 ltc1410 accuracy ic dy u w a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 100khz input signal (note 12) l 70 72.5 db 600khz input signal (note 12) l 68 71.0 db thd total harmonic distortion 100khz input signal, first 5 harmonics C 85 db 600khz input signal, first 5 harmonics l C82 C74 db peak harmonic or spurious noise 600khz input signal l C84 C74 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 84 db full power bandwidth 20 mhz full linear bandwidth (s/(n + d) 3 68db) 2.5 mhz digital i puts a d digital outputs u u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v i o = C 10 m a 4.5 v i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz high-z output leakage d11 to d0 v out = 0v to v dd , cs high l 10 m a c oz high-z output capacitance d11 to d0 cs high (note 9 ) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma i ter al refere ce characteristics u uu the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/v C 5.25v v ss C 4.75v 0.01 lsb/v v ref output resistance ? i out ? 0.1ma 2 k w comp output voltage i out = 0 4.06 v symbol parameter conditions min typ max units v dd positive supply voltage (notes 10, 11) 4.75 5.25 v v ss negative supply voltage (note 10) C 4.75 C 5.25 v i dd positive supply current cs = rd = convst = 5v l 12 16 ma nap mode shdn = 0v, nap/slp = 5v 1.5 2.3 ma sleep mode shdn = 0v, nap/slp = 0v 1 100 m a i ss negative supply current cs = rd = convst = 5v l 20 30 ma nap mode shdn = 0v, nap/slp = 5v 10 200 m a sleep mode shdn = 0v, nap/slp = 0v 1 100 m a power require e ts w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5)
4 ltc1410 power require e ts w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units p d power dissipation 160 230 mw nap mode shdn = 0v, nap/slp = 5v 7.5 12 mw sleep mode shdn = 0v, nap/slp = 0v 0.01 1 mw symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 1.25 mhz t conv conversion time l 650 750 ns t acq acquisition time l 50 100 ns t acq+conv throughput time l 800 ns (acquisition + conversion) t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 10 ns t 3 nap/slp to shdn setup time (notes 9, 10) l 10 ns t 4 shdn - to convst wake-up time (note 10) 200 ns t 5 convst low time (notes 10, 11) l 40 ns t 6 convst to busy delay c l = 25pf 10 ns l 50 ns t 7 data ready before busy - 20 35 ns l 15 ns t 8 delay between conversions (note 10) l 40 ns t 9 wait time rd after busy - (note 10) l C5 ns t 10 data access time after rd c l = 25pf 15 25 ns l 35 ns c l = 100pf 20 35 ns l 50 ns t 11 bus relinquish time 820 ns commercial l 25 ns industrial l 30 ns t 12 rd low time l t 10 ns t 13 convst high time l 40 ns t 14 aperture delay of sample-and-hold C 1.5 ns ti i g characteristics w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best results ensure that convst returns high either within 425ns after the start of the conversion or after busy rises. note 12: signal-to-noise ratio (snr) is measured at 100khz and distortion is measured at 600khz. these results are used to calculate signal-to-noise plus distortion (sinad). note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, ognd and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, v ss = C 5v, f sample = 1.25mhz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended +a in input with C a in grounded.
5 ltc1410 typical perfor m a n ce characteristics uw s/(n + d) vs input frequency and amplitude distortion vs input frequency input frequency (hz) 1k signal/(noise + distortion) (db) 80 70 60 50 40 30 20 10 0 10k 100k 1410 g01 1m 10m v in = 0db v in = 20db v in = 60db f sample = 1.25mhz input frequency (hz) 1k amplitude (db below the fundamental) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 10k 100k 1410 g03 1m 10m thd 2nd 3rd spurious-free dynamic range vs input frequency integral nonlinearity vs output code differential nonlinearity vs output code input frequency (hz) 10k spurious-free dynamic range (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100k 1m 10m 1410 g04 input common mode rejection vs input frequency input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k 1410 g09 1m 10m signal-to-noise ratio vs input frequency input frequency (hz) 1k signal-to-noise ratio (db) 80 70 60 50 40 30 20 10 0 10k 100k 1410 g02 1m 10m intermodulation distortion plot frequency (khz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 100 200 300 400 1410 g05 500 600 f sample = 1.25mhz f in1 = 88.19580078khz f in2 = 111.9995117khz power supply feedthrough vs ripple frequency ripple frequency (hz) amplitude of power supply feedthrough (db) 0 ?0 ?0 ?0 ?0 100 120 1k 100k 1m 10m 1410 g08 10k v ripple = 0.1v v ss v dd dgnd output code 0 inl error (lsb) 4096 1410 g07 1024 2048 3072 1.0 0.5 0 0.5 1.0 512 1536 2560 3504 output code 0 dnl error (lsb) 4096 1410 g06 1024 2048 3072 1.0 0.5 0 0.5 1.0 512 1536 2560 3504
6 ltc1410 pi fu ctio s uu u +a in (pin 1): positive analog input, 2.5v. Ca in (pin 2): negative analog input, 2.5v. v ref (pin 3): 2.50v reference output. refcomp (pin 4): 4.06v reference bypass pin. by- pass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. agnd (pin 5): analog ground. d11 to d4 (pins 6 to 13): three-state data outputs. dgnd (pin 14): digital ground for internal logic. tie to agnd. d3 to d0 (pins 15 to 18): three-state data outputs. ognd (pin 19): digital ground for output drivers. tie to agnd. nap/slp (pin 20): power shutdown mode. selects the mode invoked by the shdn pin. low selects sleep mode and high selects quick wake-up nap mode. fu ctio al block diagra uu w 12-bit capacitive dac comp ref amp 2k 2.5v ref refcomp (4v) c sample c sample d11 d0 busy control logic cs convst rd shdn internal clock nap/slp zeroing switches dv dd v ss av dd +a in ? in v ref agnd dgnd 12 ltc1410 ?bd + successive approximation register output latches shdn (pin 21): power shutdown input. a low logic level will invoke the shutdown mode selected by the nap/slp pin. rd (pin 22): read input. this enables the output drivers when cs is low. convst (pin 23): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 24): the chip select input must be low for the adc to recognize convst and rd inputs. busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. data valid on the rising edge of busy. v ss (pin 26): C 5v negative supply. bypass to agnd with 10 m f tantalum in parallel 0.1 m f ceramic. dv dd (pin 27): 5v positive supply. short to pin 28. av dd (pin 28): 5v positive supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic.
7 ltc1410 test circuits applicatio n s i n for m atio n wu u u conversion details the ltc1410 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the + a in and C a in inputs are connected to the sample-and-hold capacitors (c sample ) during the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum duration of 100ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches connect the c sample capacitors to ground, transferring the differential analog input charge 1k c l c l dbn (a) hi-z to v oh and v ol to v oh (b) hi-z to v ol and v oh to v ol dbn 1k 5v 1410 tc01 1k 100pf 100pf dbn (a) v oh to hi-z (b) v ol to hi-z dbn 1k 5v 1410 tc02 load circuits for access timing load circuits for output float delay onto the summing junctions. this input charge is succes- sively compared with the binarily-weighted charges sup- plied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the + a in and C a in input charges. the sar contents (a 12-bit data word) which represent the difference of + a in and C a in are loaded into the 12-bit output latches. sample hold +c sample ? sample d11 d0 zeroing switches +a in +c dac +v dac ? dac ? dac ? in 12 1410 f01 comp + output latches sar sample hold hold hold figure 1. simplified block diagram
8 ltc1410 applicatio n s i n for m atio n wu u u dynamic performance the ltc1410 has excellent high speed sampling capabil- ity. fast four transform (fft) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. frequency (khz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 100 200 300 400 1410 f02a 500 600 f sample = 1.25mhz f in = 100.098khz sfdr = 90.1db sinad = 72.4db frequency (khz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 100 200 300 400 1410 f02b 500 600 f sample = 1.25mhz f in = 599.975khz sfdr = 84.7db sinad = 71.7db figure 2b. ltc1410 nonaveraged 4096 point fft, 600khz input figure 2a. ltc1410 nonaveraged 4096 point fft, 100khz input to frequencies from above dc and below half the sampling frequency. figures 2a and 2b shows a typical spectral content with a 1.25mhz sampling rate for 100khz and 600khz inputs. the dynamic performance is excellent for input frequencies up to the nyquist limit of 625khz and beyond. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76] / 6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 1.25mhz the ltc1410 maintains very good enobs up to the nyquist input frequency of 625khz and beyond. refer to figure 3. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the adc output. the output is band limited input frequency (hz) 2 effective bits s/(n + d) (db) 4 6 8 10 10k 100k 1m 10m ltc1410 ?ta02 0 1k 12 74 68 62 56 50 f sample = 1.25mhz nyquist figure 3. effective bits and signal/(noise + distortion) vs input frequency total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vv = +++ 20 3 2 4 2 log v . . .v v 2 2 n 2 1
9 ltc1410 applicatio n s i n for m atio n wu u u where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1410 has good distortion performance up to the nyquist frequency and beyond. frequency (mhz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 100 (f b ? a ) (f a +f b ) (2f a +f b ) (f a +2f b ) (f a ) (2f a ) (f b ) (2f b ? a ) 200 300 400 1410 f05 500 600 (2f b ) f sample = 1.25mhz f in1 = 88.19580078khz f in2 = 111.9995117khz (2f a ? b ) (3f a ) (3f b ) figure 5. intermodulation distortion plot peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibel relative to the rms value of a full-scale input signal. full power and full linear bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1410 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) does not become dominated by distortion until frequen- cies far beyond nyquist. driving the analog input the differential analog inputs of the ltc1410 are easy to drive. the inputs may be driven differentially or as a single-ended input (i.e., the C a in input is grounded). the +a in and C a in inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold input frequency (hz) 1k amplitude (db below the fundamental) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 10k 100k 1410 g03 1m 10m thd 2nd 3rd figure 4. distortion vs input frequency intermodulation distortion (imd) if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a + f b ). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd f f f amplitude at ab b + () = () 20 log amplitude at f f a a
10 ltc1410 applicatio n s i n for m atio n wu u u capacitors at the end of conversion. during conversion the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the ltc1410 inputs can be driven directly. as source imped- ance increases so will acquisition time (see figure 6). for minimum acquisition time with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conver- sion starts (settling time must be 100ns for full through- put rate). source resistance ( w ) 10 acquisition time ( m s) 1 1410 f06 0.1 0.01 100 1k 10k 100k 10 figure 6. acquisition time vs source resistance choosing an input amplifier is easy if a few requirements are taken into consideration. first, choose an amplifier that has a low output impedance (< 100 w ) at the closed- loop bandwidth frequency. for example, if an amplifier is used in a gain of +1 and has a closed-loop bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 20mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. suitable devices capable of driving the adcs inputs include the lt ? 1360, lt1220, lt1223, lt1224 and lt1227 op amps. the noise and the distortion of the input amplifier must also be considered since they will add to the ltc1410 noise and distortion. the small-signal bandwidth of the sample-and-hold circuit is 20mhz. any noise that is present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is usually sufficient. for example, figure 7 shows a 1000pf capacitor from + a in to ground and a 100 w source resistor will limit the input bandwidth to 1.6mhz. simple rc filters work well for ac applications, but they will limit the transient response. for full speed operation, amplifiers with fast settling and low noise should be chosen. 1 2 3 4 5 0.1 m f 10 m f 100 w analog input 1000pf 1410 f07 +a in ? in v ref refcomp agnd ltc1410 figure 7. rc input filter internal reference the ltc1410 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3). see figure 8a. a 2k resistor is in series with the output so that it can be 1 2 3 +a in ? in ltc1410 4.06v 0.1 m f 10 m f r2 40k r1 2k analog input 2.500v 1410 f08a refcomp agnd v ref 4 5 r3 64k + bandgap reference figure 8a. ltc1410 reference circuit
11 ltc1410 applicatio n s i n for m atio n wu u u 1 2 3 4 5 0.1 m f 10 m f analog input 1410 f08b lt1019a-2.5 v out v in 5v +a in ? in v ref refcomp agnd ltc1410 figure 8b. using the lt1019-2.5 as an external reference easily overdriven in applications where an external refer- ence is required. the reference amplifier provides buffer- ing between the internal reference and the capacitive dac. the reference amplifier compensation pin refcomp (pin 4), must be bypassed with a capacitor to ground. the reference amplifier is stable with capacitors of 1 m f or greater. for the best noise performance, a 10 m f tantalum in parallel with 0.1 m f ceramic is recommended. the v ref pin can be driven with an external reference (figure 8b), a dac or other means to provide input span adjustment. the v ref should be kept in the range of 2.25v to 2.75v for specified linearity. full-scale and offset adjustment figure 9 shows the ideal input/output characteristics for the ltc1410. the code transitions occur midway between successive integer lsb values (i.e., C fs + 0.5lsb, C fs + 1.5lsb, C fs + 2.5lsb, . . . fs C 1.5lsb, fs C 0.5lsb).the output is twos complement binary with 1lsb = [(+fs) C (C fs)]/4096 = 5v/4096 = 1.22mv. in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 10 shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the C a in input. for zero offset error apply C 0.61mv (i.e., C 0.5lsb) at +a in and adjust the offset at the C a in input until the output code flickers between 0000 0000 0000 and 1111 1111 1111. for full-scale adjust- ment, an input voltage of 2.49817v (fs C 1.5lsbs) is applied to a in and r2 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1410, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. particular care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. analog input 1410 f10 1 2 3 r4 100 w r2 50k r3 47k ?v r6 24k r1 50k r5 47k 4 5 0.1 m f 10 m f +a in ? in v ref refcomp agnd ltc1410 figure 10. offset and full-scale adjust circuit input voltage, (+a in ) ?(a in ) (v) 0v output code ? lsb 1410 f09 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs ?lsb fs fs = 2.5v 1lsb = 2fs 4096 figure 9. ltc1410 transfer characteristics
12 ltc1410 applicatio n s i n for m atio n wu u u high quality tantalum and ceramic bypass capacitors should be used at the v dd , v ss and refcomp pins as shown in the typical application on the first page of this data sheet. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1410 has differential inputs to minimize noise coupling. common mode noise on the + a in and C a in leads will be rejected by the input cmrr. the C a in input can be used as a ground sense for the + a in input; the ltc1410 will hold and convert the difference voltage between + a in and C a in . the leads to + a in (pin 1) and C a in (pin 2) should be kept as short as possible. in applications where this is not possible, the + a in and C a in traces should be run side by side to equalize coupling. a single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 5 (agnd) or as close as possible to the adc. pin 14 and pin 19 (adcs dgnd) and all other analog grounds should be connected to this single analog ground point. no other digital grounds should be connected to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be elimi- nated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to iso- late the adc data bus. digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a con- version. internal clock the a/d converter has an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 0.65 m s and a maximum conversion time over the full operating temperature range of 0.75 m s. no external adjustments are required. the guaranteed maximum ac- quisition time is 100ns. in addition, throughput time of 800ns and a minimum sampling rate of 1.25msps is guaranteed. 1410 f11 digital system 0.1 m f analog input circuitry 4 2 26 19 14 1 0.1 m f 10 m f 10 m f + 0.1 m f 28 27 10 m f + a in a in agnd refcomp av dd v ss dv dd dgnd ognd ltc1410 figure 11. power supply grounding practice
13 ltc1410 applicatio n s i n for m atio n wu u u power shutdown the ltc1410 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. in sleep mode all bias currents are shut down and only leakage current re- mains CC about 1 m a. wake-up time from sleep mode is t 3 nap/slp shdn 1410 f12a figure 12a. nap/slp to shdn timing figure 12b. shdn to convst wake-up timing much slower since the reference circuit must power up and settle to 0.01% for full 12-bit accuracy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 10ms with the recommended 10 m f capacitor. shutdown is controlled by pin 21 (shdn), the adc is in shutdown when it is low. the shutdown mode is selected with pin 20 (nap/slp); high selects nap. t 2 t 1 cs convst rd 1410 f12 t 4 shdn convst 1410 f12b figure 13. cs to convst setup timing timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a logic 0 applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. figures 14 through 18 show several different modes of operation. in modes 1a and 1b (figures 14 and 15) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 16) cs is tied low. the falling edge of convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. in slow memory and rom modes (figures 17 and 18) cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor applies a logic low to rd (= convst), starting the conversion. busy goes low forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results ap- pear on the data outputs; busy goes high releasing the processor and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion.
14 ltc1410 figure 14. mode 1a. convst starts a conversion. data outputs always enabled (convst = ) figure 15. mode 1b. convst starts a conversion. data outputs always enabled (convst = ) data (n ?1) db11 to db0 convst busy 1410 f15 t conv t 6 t 13 t 7 cs = rd = 0 data n db11 to db0 data (n + 1) db11 to db0 data t 5 t 6 t 8 convst busy 1410 f16 t 5 t conv t 8 t 13 t 6 t 9 t 12 data n db11 to db0 t 11 t 10 rd data figure 16. mode 2. convst starts a conversion. data is read by rd applicatio n s i n for m atio n wu u u data n db11 to db0 data (n + 1) db11 to db0 data (n ?1) db11 to db0 convst cs = rd = 0 busy 1410 f14 t 5 t conv t 6 t 8 t 7 data
15 ltc1410 u s a o pp l ic at i wu u i for atio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. rd = convst busy 1410 f18 t conv t 6 data (n ?1) db11 to db0 data data n db11 to db0 t 10 t 11 t 8 figure 18. rom mode timing rd = convst busy 1410 f17 t conv t 6 data (n ?1) db11 to db0 data data n db11 to db0 data (n + 1) db11-db0 data n db11 to db0 t 11 t 8 t 10 t 7 figure 17. slow memory mode timing u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640)
16 ltc1410 1410fa lt/tp 0399 2k rev a ? printed in usa u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. sw package 28-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) related parts 12-bit sampling a/d converters part number description comments ltc1273/75/76 complete 5v sampling 12-bit adcs lower power and cost effective for f sample 300ksps with 70db sinad at nyquist ltc1274/77 low power 12-bit adcs with nap lowest power for f sample 100ksps and sleep mode shutdown ltc1278/79 high speed sampling 12-bit adcs cost effective 12-bit adcs CC best for 2-pair hdsl, with shutdown f sample 500ksps/600ksps ltc1282 complete 3v 12-bit adcs with fully specified for 3v-powered applications, f sample 140ksps 12mw power dissipation ? linear technology corporation 1995 s28 (wide) 0996 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ note 1 0.697 ?0.712* (17.70 ?18.08) 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 25 26 11 12 22 21 20 19 18 17 16 15 23 24 14 13 27 28 note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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